This invention relates generally to computer systems and more particularly to distribution of clock signals and operation of synchronous busses in a synchronous computer system.
As it is known in the art, one type of computer system generally referred to as a synchronous computer system having a synchronous bus includes a plurality of modules of different functionality coupled together via the system bus. Each of said modules in a synchronous computer system operate by a synchronization signal which is generally referred to as a clock signal.
As computer systems operated at higher clock frequencies fostered by the development of faster microprocessors, a requirement arises that data transfers between modules and within a module increase concomitant therewith. For very fast or high frequency computer systems employing high frequency clock signals, the skew, that is the difference in the time between a asserting edges of a pair of clock signals becomes a significant factor for proper operation of a computer system.
Although synchronous computer systems having a synchronous bus are known generally, multi-processor computer systems employing a synchronous bus present difficulties. One of the difficulties presented is that often the processors or microprocessors used in the multi-processor computer system operate with clock frequencies which are substantially higher than the clock frequency used to operate the synchronous bus. This presents a problem in ensuring that the entire process operates synchronously. This problem is a direct result of clock skew mentioned above.
For proper operation of a computer system, clock signals should arrive at the point where the clock is used on the associated integrated circuit at the same time. The degree to which clock signals arrive at different times or on different modules in a computer system is an indication of the clock skew across the computer system. If a clock signal arrives at a logic circuit on a module earlier than other clock signals to other logic circuits on the module, reliable data transfer may not occur since the earlier arrived signal may assert its edge before data presented to the logic circuit are valid. Conversely, circuits where the clock signal arrives later may assert its edge after data have become invalid.
Thus, the skew provided in a clock system directly increases the amount of time that data must remain stable on a bus to ensure that reliable data transmissions occur. Increasing the amount of time in which the data is required to remain on the bus provides a concomitant decrease in the data transfer rate of the bus, and thus, reduces the speed of the bus in the overall computer system.
Clock skew is related to various factors including variations in propagation delays amongst clock receiver circuits and velocity factor differences in module etchings of a computer system bus interconnect. Furthermore, clock skew can also be introduced by other factors such as processing variations from integrated circuit to integrated circuit, temperature variations across different integrated circuits in the computer system as well as variations due to voltage loading effects.
A second problem also arises in synchronous computer systems in which upgrades to the computer system are desirable. For example, it is well-known that current microprocessor technology generally develops a basic microprocessor which operates using a basic clock speed. As the processing technology improves for the particular microprocessor, however, often times the clock speed of the microprocessor can be increased often times by a factor of two or more. It would be desirable to be able to insert a faster microprocessor in place of a slower microprocessor and still maintain all functionality in the computer system.
Often times, however, this is not possible since not all components connected to the synchronous computer system bus operate using an approach which allows such devices to operate using different clock signals.